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Versatile, wide range Multiprotocol SerDes solutions for challenging standards and applications including DisplayPort and PCIe5 (Video in Mandarin, PDF in English)

January 03, 2022

At the CSIA-ICCAD 2020 Annual Conference we presented a paper titled "Versatile, wide range Multiprotocol SerDes solutions for challenging standards and applications including DisplayPort and PCIe5" with the following sections:

• Silicon Creations introduction
• SerDes history (explanation for why serial links replaced parallel busses in a brief history of SerDes links)
• Multiprotocol SerDes PMAs (Silicon Creations IPs supporting Multiprotocol SerDes links with few compromises -- a portfolio created first for a famous FPGA - the PolarFire and summary of our ultra-low latency variant)
• Selected test results (from our 12nm FinFET SerDes PMA) 

Abstract:  

The data communications requirements of many SoC’s can be met with “shrink-wrapped” SerDes designed to meet the requirements for high-volume standards such as Ethernet, PCIe, USB and SATA. However, these SerDes solutions targeting high volume protocols are rarely customized beyond the strict requirements of the standards and do not meet the requirements of more demanding standards.

Silicon Creations developed the Multiprotocol SerDes solution in UMC 28HLP for Microsemi’s PolarFire FPGA. This PMA IP has very competitive Power, Performance and Area and supports over 30 protocols at speeds from 143Mbps to 12.7Gbps including PCIe, JESD204, CPRI, DisplayPort, SMPTE SDI, G/EPON, 10G-KR Ethernet and custom low-latency chip-chip interfaces. We have ported this IP to TSMC and GF 40LP, 40G, TSMC 12FFC/16FFC and GF12LP+ (to 32.75Gbps).

The PMA includes a number of features not offered by others, including (i) extremely low loop latency down to 23UI, (ii) software configurable burst mode CDR locking in less than 160 UI and (iii) fast CDR capable of meeting the demanding 3G-SDI Pathological Pattern and Display Port Jitter Tolerance requirements with margin. The adaptive equalization algorithm is supplied as an RTL state machine proven over hundreds of PolarFire FPGA customer applications and supports software control. A non-destructive eye monitor enables continuous link quality analysis for time variant channels and safety critical applications.

This paper provides a historical review of SerDes developments and standards beginning with the authors’ work in the 1990’s and places our SerDes PMA within this context, comparing some key figures of merit. The benefits conveyed by the differentiated features are highlighted with typical silicon test results shown and compared to simulations.